1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor (TFT) array substrate, and more particularly, to a method of fabricating a TFT array substrate having improved reliability.
2. Description of the Related Art
A TFT array substrate includes a p-channel metal-oxide semiconductor (PMOS) TFT, an n-channel metal-oxide semiconductor (NMOS) TFT, and a storage capacitor. According to the method of fabricating a TFT array substrate, a buffer layer is formed on a substrate. On the substrate on which the buffer layer is formed, a semiconductor layer of a PMOS TFT, a semiconductor layer of an NMOS TFT, and a lower electrode pattern of a storage capacitor are formed by a first mask process. Subsequently, a gate insulating layer is formed on the entire surface of the substrate on which the semiconductor layer of the PMOS TFT, the semiconductor layer of the NMOS TFT, and the lower electrode pattern of the storage capacitor are formed.
On the substrate on which the gate insulating layer formed, a photoresist pattern is formed by a photolithography process using a second mask to cover the entire surface of the semiconductor layer of the PMOS TFT and expose regions, in which a source region and a drain region of the NMOS TFT will be formed, in the semiconductor layer of the NMOS TFT and the lower electrode pattern of the storage capacitor. Subsequently, N+ ions, such as phosphor (P), arsenic (As), antimony (Sb), bismuth (Bi), etc. are injected into the exposed semiconductor layer of the NMOS TFT and the exposed lower electrode pattern of the storage capacitor using the photoresist pattern as a mask, thereby forming a source region and a drain region of the NMOS TFT and a lower electrode of the storage capacitor. Then, the photoresist pattern is removed by a strip process.
On the substrate on which the source and drain regions of the NMOS TFT and the lower electrode of the storage capacitor are formed, a gate electrode of the PMOS TFT overlapping a region in which a channel of the PMOS TFT will be formed, a gate electrode of the NMOS TFT overlapping a region in which a channel of the NMOS TFT will be formed, and an upper electrode of the storage capacitor overlapping the lower electrode of the storage capacitor are formed by a third mask process. Here, the gate electrode of the NMOS TFT is formed to have a smaller width than the photoresist pattern for forming the source region and the drain region of the NMOS TFT. Subsequently, using the gate electrode of the PMOS TFT, the gate electrode of the NMOS transistor, and the upper electrode of the storage capacitor as masks, N− ions are injected into the exposed semiconductor layer of the PMOS TFT and the exposed semiconductor layer of the NMOS TFT, thereby defining the channel of the PMOS TFT overlapping the gate electrode of the PMOS TFT and the channel of the NMOS TFT overlapping the gate electrode of the NMOS TFT, and forming lightly doped drain (LDD) regions of the NMOS TFT between the channel and the source and drain regions of the NMOS TFT.
On the substrate having the LDD regions of the NMOS TFT formed thereon, a photoresist pattern covering the entire surface of the semiconductor layer of the NMOS TFT is formed by a photolithography process using a fourth mask. Subsequently, using the photoresist pattern as a mask, P+ ions, such as boron (B), aluminum (Al), gallium (Ga), indium (In), etc., are injected into regions, in which a source region and a drain region of the PMOS TFT will be formed, in the exposed semiconductor layer of the PMOS TFT, thereby forming a source region and a drain region of the PMOS TFT. Then, the photoresist pattern is removed by a strip process.
After an interlayer insulating layer is formed on the entire surface of the substrate having the source region and the drain region of the PMOS TFT formed thereon, source contact holes and drain contact holes are formed by a fifth mask process to penetrate the gate insulating layer and the interlayer insulating layer and expose the source and drain regions of the PMOS TFT and the source and drain regions of the NMOS TFT. Subsequently, a source electrode and a drain electrode of the PMOS TFT connected with the source and drain regions of the PMOS TFT, and a source electrode and a drain electrode of the NMOS TFT connected with the source and drain regions of the NMOS TFT are formed by a sixth mask process.
As described above, the method of fabricating a TFT array substrate includes photolithography processes to form the photoresist patterns for N+ ion injection, formation of the gate electrodes, and P+ ion injection after the gate insulating layer is formed and before the interlayer insulating layer is formed. The photoresist patterns include a large number of mobile ions therein. In the processes of N+ ion injection, formation of the gate electrodes, and P+ ion injection, the mobile ions move to the semiconductor layers of the PMOS and NMOS TFTs through the gate insulating layer. Then, the moved mobile ions affect the operation of the PMOS and NMOS TFTs. Consequently, the PMOS and NMOS TFTs are affected in their operations by the mobile ions moved from the photoresist patterns to the semiconductor layers of the PMOS and NMOS TFTs, thus deteriorating the reliability of the PMOS and NMOS TFTs.
In addition, another method of fabricating a TFT array substrate includes forming a lower electrode of a storage capacitor by injecting N+ ions, thus requiring a photolithography process for N+ ion injection so as to form a lower electrode pattern of the storage capacitor, which is formed together with a semiconductor layer of a PMOS TFT, as the lower electrode of the storage capacitor. Therefore, after a gate insulating layer is formed and before an interlayer insulating layer is formed, a method of fabricating a PMOS TFT includes a photolithography process for N+ ion injection to form the lower electrode pattern as the lower electrode and a photolithography process for forming a gate electrode of the PMOS TFT and P+ ion injection.
In this other method of fabricating a TFT array substrate includes photolithography processes after the gate insulating layer is formed and before the interlayer insulating layer is formed. Consequently, as described above, the PMOS TFT is affected in its operation by the mobile ions moved from the photoresist pattern to the gate insulating layer, thus deteriorating the reliability of the PMOS TFT. Furthermore, since the lower electrode of the storage capacitor is formed by injecting N+ ions, the process of fabricating a PMOS TFT is complicated.